Asian power broker takes UltraSoc debugging technology
Andes Technology, the leading and established CPU IP supplier in Asia, has adopted Cambridge-based UltraSoC’s advanced embedded analytics technology for use in its AndesCore range of RISC-V processors.
Andes will leverage UltraSoC’s unique intellectual property offering, including the industry’s only commercial RISC-V processor trace solution, to accelerate development and enhance debugging of embedded products for sophisticated applications including Artificial Intelligence, computer vision, network controllers, and storage.
The two companies will collaborate to demonstrate a complete RISC-V development, debug, and trace flow at the upcoming RISC-V Workshop – May 7-10, in Spain.
UltraSoC is the only company offering a commercial RISC-V development environment, with SoC analytics, processor trace and other options available to meet the needs of end customers.
A pioneer in the industry, UltraSoC developed processor trace for RISC-V in 2017 and shortly afterwards offered its trace specification for use by the RISC-V Foundation as part of its standardisation effort.
The company remains fully committed to supporting the RISC-V Foundation standard run-control/debug and the proposed processor trace format, in line with its wider strategy of providing integrated debug and development solutions for any processor architecture, including Arm, Cadence/Tensilica, CEVA and MIPS.
Andes’ cores are based on the high-performance AndeStarTM V5 32-bit and 64-bit architectures. The partnership with UltraSoC allows customers for Andes V5 N25 and NX25 processors to have advanced embedded analytics capabilities integrated as an option. Customers using Andes’ high-performance 32 and 64-bit processor cores gain access to UltraSoC’s SoC analytics and debug IP in addition to RISC-V processor trace, which together give designers full visibility not only of the performance of the core but into the operation of the entire system.
Andes has adopted RISC-V for its fifth generation processor architecture, the AndeStar V5, and launched two high-end processor cores in its AndesCoreTM family of configurable processor IP: the 32-bit N25 and the 64-bit NX25.
Both are RISC-V based and deliver in excess of 3.4 CoreMark/MHz, with gate counts as small as 30K (N25) and 50K (NX25), and a maximum clock rate of 1.1 GHz when using TSMC’s 28nm HPC process.
The N25 and NX25 are both ideal for high-speed control tasks, and customers choosing either core will benefit from access to UltraSoC’s embedded intelligence.
Charlie Su, CTO and senior VP of Andes, said: “Choosing UltraSoC as our preferred partner for embedded analytics, trace and validation gives our customers an advanced development environment with insight into SoC operations and processor execution without disturbing target behaviour.
“UltraSoC has shown itself to be committed to the development of the RISC-V ecosystem and hence it is clearly the best partner for our V5 RISC-V architecture.”
Rupert Baines, CEO of UltraSoC added: “We are delighted to be working with Andes on its innovative processor cores for RISC-V and collaborating with mutual customers on implementations which utilise the power of its leading V5 AndeStar architecture and enable designers full access to the system with the support of UltraSoC’s SoC analytics and debug IP, and processor trace."
• PHOTOGRAPH SHOWS: Rupert Baines