Cambridge scale-ups join forces to protect hardware from cyber attacks
Two fast-scaling Cambridge technology companies, Agile Analog and UltraSoC, have formed a collaboration to protect hardware infrastructure from cyber attacks.
The alliance combines UltraSoC’s embedded on-chip analytics with Agile Analog’s advanced on-chip analog monitoring IP to detect and prevent ‘analog interference’ cyber attacks that circumvent traditional security measures by tampering with underlying systems such as power supply levels or clock signals.
Spearheaded by senior ex-Arm employees, Agile Analog attracted high profile financial backers Delin Ventures, firstminute Capital and MMC Ventures in a $5 million Pre-A funding round last May. This was followed up with around £500k from Innovate UK to accelerate new product development.
UltraSoC closed a substantially oversubscribed £5 million equity funding round in June 2019 in which cybersecurity-focused German venture capital firm eCAPITAL, and Seraphim Capital, a specialist investor in the space ecosystem, joined existing UltraSoC investors Indaco Venture Partners, Octopus Ventures, Oxford Capital, Techgate, and business angel Guillaume d’Eyssautier.
Agile Analog’s AI-driven platform replaces an existing manual design process that has not fundamentally changed in 60 years. Former Arm engineering executive Tim Ramsdale is chief executive and Pete Hutton – Arm’s former president of product – is chair of the UK business.
Agile Analog offers a parallel range of “smart” monitors in the analog domain, such as voltage, temperature and timing sensors to detect side-channel attacks or anomalous behaviour that could indicate a cyber attack.
The combination of system-level digital monitoring and analog capabilities will enable a holistic approach to hardware-based cybersecurity.
These types of side-channel attacks, such as voltage and clock glitching, brownouts and temperature variations, can be used to gain access to a chip’s internal circuitry, which makes UltraSoC’s hardware based security essential in monitoring and defending against these attacks where hackers may exploit side-channel vulnerabilities to launch a brute force attack.
UltraSoC’s latest cybersecurity products monitor the functional behavior of digital circuitry, adding an extra layer of defense-in-depth to the security landscape, and detecting and mitigating cyber threats at hardware speed.
Gajinder Panesar, CTO at UltraSoC, commented: “Agile Analog has some truly unique technology that’s invaluable in monitoring the underlying analog behaviour of an SoC for potential signs of suspicious or unexpected activity. We believe that partnerships like this are key to enabling a holistic secure embedded cybersecurity architecture with monitoring capable of delivering from fab to field.”
Mike Hulse, CTO at Agile Analog, added: “We share UltraSoC’s vision of a holistic embedded cybersecurity eco-system.
“Working together will allow us to move a step closer to that vision. Security is one of the key pain points faced by every electronics manufacturer today – particularly in industries such as automotive.
“The complementary nature of our technologies – UltraSoC offering system-level functional monitoring, and Agile Analog looking at underlying analog behavior – makes our products a natural fit for cybersecurity applications.”
UltraSoC embeds transaction-aware hardware monitors into the digital infrastructure of an SoC. These are interconnected via a message-based architecture, allowing the implementation of sophisticated system-wide anomaly detection and mitigation measures.
The company’s Bus Sentinel and CAN Sentinel hardware modules, for example, can identify and instantaneously block suspicious communications within the chip. Bus Sentinel was awarded a Best in Show award in the security category at the recent Embedded World 2020 event. The partnership with Agile Analog will integrate data from analog monitors (such as clock, voltage and temperature monitors) into the UltraSoC cybersecurity infrastructure, enabling even more sophisticated anomaly detection schemes.